The present invention relates to a technology for manufacturing a semiconductor wafer and a semiconductor device, and particularly to a technology effective for application to semiconductor devices formed using a semiconductor wafer having a large bore diameter.
As one means for achieving a reduction in the cost of a semiconductor device (semiconductor integrated circuit device), a semiconductor device manufacturing method using a large bore-diameter semiconductor wafer has been discussed to increase the acquired number of devices (chips) manufactured from one sheet of semiconductor wafer.
On the other hand, as will be further described in detail, there is a need to thin a substrate (semiconductor wafer in its manufacturing process) with a view toward maintaining the performance of a semiconductor device and improving it.
Accordingly, various contrivances have been made to meet the requirements for an increase in the diameter of the semiconductor wafer and its thinning.
A technology for leaving a wafer peripheral portion on both main surfaces of a silicon wafer thickened to increase its diameter and enhance its mechanical strength, for example, and forming first and second concave portions over a wide area, thereby thinning the thickness of a high resistivity layer and improving the speed of response of a semiconductor device has been disclosed in, for example, Unexamined Patent Publication No. Hei 11(1999)-121466.
A technology for avoiding the leaving of a resist in a concave portion defined in a main surface of a wafer at the formation of a low resistivity layer, reducing variations in the characteristic of each device or element and thereby enhancing yields has been disclosed in Unexamined Patent Publication No. Hei 2000-40833. The concave portion is provided to thin the thickness of the wafer and improve the speed of response or the like of a semiconductor device.
Further, a technology for forming cutting trenches wider than lines cut by a dicing saw to thereby achieve a reduction in damage at cutting of semiconductor chips has been disclosed in Unexamined Patent Publication No. Hei 10(1998)-83976.
A technology for defining or making up inverted triangular trenches in scribe lines as dicing line trenches or grooves over a wafer substrate to thereby prevent crack phenomena of chips at cutting of the scribe lines and displacements on dicing has been disclosed in Unexamined Patent Publication No. Hei 9(1997)-330891.
The present inventors are involved in the investigation and development of a semiconductor device, particularly, a semiconductor integrated circuit device having insulated gate bipolar transistors (IGBTs). The present inventors have studied a method of manufacturing semiconductor devices using a semiconductor wafer of a large bore diameter, e.g., 8 inches (where 1 inch=2.54 cm) or more in order to increase the acquired number of devices (chips) manufactured from one sheet of semiconductor wafer.
In order to (1) enhance a radiation characteristic of the semiconductor device and (2) achieve thinning of a package or achieve layering of a semiconductor chip, there is a need to thin a substrate (semiconductor wafer in its manufacturing process). In a semiconductor element in which a current flows in a vertical direction with respect to the substrate as in the IGBT, the thickness of the substrate greatly affects the performance of the semiconductor element.
Thus, there is a need to use a semiconductor wafer thin and large in bore diameter. However, such a semiconductor wafer has the following problems.
Namely, 1) the semiconductor wafer is apt to break and difficult to handle. 2) The semiconductor wafer per se is low in mechanical strength and apt to produce warpage and distortion. Such warpage and distortion further increase with the stress of a film laminated on the semiconductor wafer, and hence the semiconductor wafer is apt to break during a manufacturing process. This leads to the occurrence of a crystal defect. Further, the semiconductor wafer subsequent to the occurrence of the warpage and distortion is hard to be focalized in a photolithography process, for example. This affects the manufacture of patterns constituting elements. When such an apparatus as to absorb and hold the semiconductor wafer is used, it is not possible to absorb and fix the semiconductor wafer. Thus, a subsequent process cannot be performed. Further, the conveying of the semiconductor wafer also falls into difficulties. 3) Particularly when the semiconductor wafer is cut and brought into fractionization (dicing) every chips at the final stage of a semiconductor device manufacturing process, a mechanical stress is applied to the semiconductor wafer and hence the semiconductor wafer is apt to break. Since the dicing is carried out at the final stage of the semiconductor device manufacturing process, it exerts a large influence on product yields and a TAT (turn around time).
With the promotion of an increase in the bore diameter of the semiconductor wafer, a certain degree of thickness is needed to hold the strength of the semiconductor wafer per se. It is said that the above 8 inch semiconductor wafer needs a thickness of about 1 mm, for example.
Thus, it is difficult to form a large-diameter semiconductor wafer with a thin thickness equal to a substrate, which is required for a final product and manufacture each semiconductor device by using the semiconductor wafer. In its manufacturing process, a step for effecting polishing or the like on the semiconductor wafer from its back surface to thereby reduce its thickness is required.
However, the thin semiconductor wafer involves a problem that it is apt to break, for example, as described above. There is a need to discuss a method for thinning processing, its timing, etc. in various ways in consideration of the semiconductor device manufacturing process.
An object of the present invention is to maintain the strength of a semiconductor wafer even after thinning of the semiconductor wafer.
Another object of the present invention is to maintain the strength of a semiconductor wafer even after thinning of the semiconductor wafer to thereby reduce warpage and cracking of the semiconductor wafer. Further, the present invention aims to make it easy to carry out a process subsequent to the thinning of the semiconductor wafer.
A further object of the present invention is to improve the characteristic of a semiconductor device, and enhance its yields and TAT.
The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of representative ones of the inventions disclosed in the present application will be described in brief as follows:
(1) There is provided a semiconductor device manufacturing method of the present invention, wherein an internal area of a back surface of a semiconductor wafer is polished to form a protrusion at an outer peripheral portion of the back surface of the semiconductor wafer, the semiconductor wafer is thereafter mounted on a support table whose surface is smaller than the internal area of the semiconductor wafer, and the internal area of the back surface of the semiconductor wafer is supported by the support table, and scribe areas of the semiconductor wafer are cut.
(2) There is provided a semiconductor device manufacturing method of the present invention, wherein semiconductor elements, wirings, etc. are formed on chip areas of a semiconductor wafer, a protective film corresponding to an insulating film of a top layer for covering these is formed over these, an internal area of a back surface of the semiconductor wafer is polished to form a protrusion at an outer peripheral portion of the back surface of the semiconductor wafer, the semiconductor wafer is thereafter supported on a support table whose surface is smaller than the internal area of the semiconductor wafer, and the internal area of the back surface of the semiconductor wafer is supported by the support table, whereby processing of the semiconductor, e.g., dicing and deposition are carried out. A step for polishing the internal area of the back surface of the semiconductor wafer is not necessarily limited to after the formation of the passivation film. Such a step may be performed between the step of forming the semiconductor elements and wirings and the step of forming the protective film. After the polishing of the internal area of the back surface of the semiconductor wafer, ion implantation and deposition or growth may be effected on the back surface of the semiconductor wafer.
(3) There is provided a semiconductor wafer having (a) a plurality of chip areas respectively comparted by scribe areas, and an internal area of a back surface thereof, which is recessed as viewed from an outer peripheral portion thereof, wherein a diameter (d4) of the internal area is larger than a diameter (d2) of a minimum circle surrounding the plurality of chip areas, (b) semiconductor elements are formed in the chip areas, and (c) trenches are formed on the scribe areas of the surface of the semiconductor wafer.
In the semiconductor wafer, each of the semiconductor elements formed in the plurality of chip areas of the (b) includes:
(b1) a first insulating film formed over the chip areas;
(b2) a gate electrode formed over the first insulating film;
(b3) a first semiconductor region of first conductivity type formed in the chip area on both sides of the gate electrode;
(b4) a second semiconductor region of second conductivity type opposite to the first conductivity type, which is formed in the first semiconductor region;
(b5) a second insulating film formed over the gate electrode and having openings over the second semiconductor region;
(b6) a first conductive film formed over the second insulating film including the top of the second semiconductor region;
(b7) a protective film formed over the first conductive film and corresponding to an insulating film of a top layer for covering the first conductive film;
(b8) a third semiconductor region of the first conductivity type formed on the back surface of the semiconductor wafer; and
(b9) a second conductive film formed on the back surface of the semiconductor wafer.
In the semiconductor wafer, an area corresponding to the surface of the semiconductor wafer and including the plurality of chip areas is formed lower than an outer peripheral portion of the surface of the semiconductor wafer, and the height of the outer peripheral portion is higher than the protective film corresponding to the insulating film of the top layer for covering an upper portion of each of the semiconductor elements.
There is provided a semiconductor wafer comprising:
(a) a plurality of chip areas respectively comparted by scribe areas;
(b) a ring-shaped member whose inside diameter (d5) is larger than a diameter (d2) of a minimum circle surrounding the plurality of chip areas, said ring-shaped member being bonded to an outer peripheral portion of a back surface of the semiconductor wafer;
(c) semiconductor elements formed on the chip areas; and
(d) trenches formed over the scribe areas of the surface of the semiconductor wafer.